GaAs Wafer Electroplating: Process Technology Overview

Gallium arsenide is a III-V compound semiconductor widely used in RF power devices, microwave chips, infrared lasers, GaAs solar cells and through-wafer via (TWV) interconnects. GaAs is brittle and chemically active, and is easily attacked by acids and alkalis. Electroplating on GaAs is mainly gold plating, used for thick metal electrodes, backside ground, via filling and heat-spreading conductive layers; silver and nickel are plated in a few cases. Compared with silicon wafer plating, the main difficulties of GaAs plating are electrochemical corrosion of the substrate, seed-layer adhesion control, step coverage in blind and through vias, warpage of thinned wafers, and control of deposit stress.

1. Main applications

1. Thick backside gold (mainstream for RF devices): after the GaAs wafer is thinned, a seed layer is sputtered on the back and 3-8 μm Au is plated as the ground electrode and heat-spreading layer, connecting the front and back of the chip through TWVs.

2. Through-wafer via plating: blind or through vias are etched in the wafer and plated with gold, connecting front-side devices to backside metal and reducing parasitic inductance in RF chips.

3. Bump plating: gold bumps for flip-chip bonding of GaAs chips.

4. Optoelectronic devices / space GaAs solar cells: electrodes are thickened with plated Au and Ag to lower series resistance and raise cell output.

2. Complete process flow

Starting point: front-side device processing complete → temporary bonding to a carrier → backside grinding and thinning (typically 50-150 μm) → backside via etch (TWV process) → electroplating → post-treatment → debonding.

1. Pre-clean (the most critical step, preventing GaAs corrosion and crater defects)

GaAs corrodes electrochemically very easily in strong acids or alkalis, producing crater defects (seed-layer blistering and peeling).

1. Plasma clean: removes organic contamination;

2. Clean in dilute weakly alkaline solution; never soak in strong acid;

3. Thorough wetting in deionised water and vacuum pre-wet to drive bubbles out of blind vias and avoid unplated vias.

Risk: ammonia/hydrogen peroxide cleaning chemistry causes galvanic corrosion of the seed layer, leading to craters and uneven deposits; soak time and mixing ratio must be tightly controlled.

2. Sputtered seed layer (the conductive base that decides deposit adhesion)

Plating needs a conductive seed layer, deposited by magnetron sputtering or e-beam evaporation. Classic stacks:

• TiW/Au: TiW is the barrier and adhesion layer, Au the conductive seed for plating; TiW ≈ 50-100 nm, Au seed 80-150 nm.
• Improved NiV/TiW/Au: further improves adhesion at the GaAs-metal interface, suppresses intermetallic formation and prevents metal peeling.

Seed-layer requirements: no pinholes and a uniform film. A pinhole lets the plating solution reach the GaAs substrate directly, causing electrochemical corrosion and scrap.

3. Plating chemistry (GaAs uses sulphite gold almost exclusively)

Cyanide gold cannot be used on GaAs: alkaline cyanide attacks the GaAs substrate. Sodium gold sulphite bath (weakly alkaline):

• Main salt: sodium gold sulphite, Au content 10-15 g/L
• pH: 7.5-8.5 (strict window); too low corrodes GaAs, too high gives rough, high-stress deposits
• Temperature: 50-60 ℃
• Conducting salts, brighteners, grain refiners;
• Oxygen must be excluded: sulphite oxidises easily, shortening bath life.

4. Plating mode: DC vs pulse / periodic reverse plating

1. DC plating: simple equipment. Drawbacks: limited ion diffusion into blind and through vias, thin deposits at the via bottom and poor step coverage; at high current density the grains are coarse and the stress high.

2. Pulse plating (the mainstream production approach): alternating high and low current pulses. The high current nucleates, the low current lets gold ions diffuse into the micro-vias, markedly improving step coverage, refining the grain, lowering surface roughness and deposit stress, and suiting TWV filling.

Equipment: horizontal plating tools dedicated to compound semiconductors, with wafer rotation and forced spray circulation of the bath; a porous anode optimises the flow field, thins the diffusion layer and improves uniformity inside the vias; compatible with 4/6-inch GaAs wafers, with nitrogen blanketing to protect the bath from air.

5. Post-treatment

1. Thorough overflow rinse after plating to remove residual sulphite bath;

2. Low-temperature drying; no high-temperature baking, to avoid warping the thin GaAs wafer;

3. Optional: backside lithography and metal etch to form scribe lanes;

4. Debond to complete wafer processing.

3. Key process difficulties and failure modes

1. Electrochemical corrosion of the GaAs substrate: plating or cleaning solution reaches GaAs through seed-layer pinholes and causes galvanic corrosion, giving craters, pitting and holes in the substrate, and scrap. Countermeasures: seed-layer quality control; strict pH control; thorough pre-wet; avoid immersing the wafer while energised; optimise the pre-clean chemistry and time.

2. Insufficient step coverage in TWVs: in high-aspect-ratio vias gold-ion diffusion is limited and the via bottom plates far thinner than the surface, especially with DC plating. Countermeasures: pulse plating; stronger bath agitation and circulation; wafer rotation; optimised anode flow field; lower limiting current density and a thinner diffusion layer.

3. Deposit stress and wafer warpage: thinned GaAs has very low mechanical strength, and stress in thick gold warps the wafer, disturbing later lithography and dicing. Countermeasures: optimise pulse parameters and brightener content; control deposit thickness; reduce internal stress; control heat-treatment temperature.

4. Seed-layer / deposit peeling: adhesion between GaAs and metal is poor and the metal peels after thermal cycling. Countermeasures: optimised seed stack (NiV/TiW/Au); strict removal of native GaAs oxide; optimised sputter parameters; avoid excessive chemical attack on the substrate surface.

5. Rough deposits and gold nodules: excessive current density, an aged bath or contamination produce raised particles on the surface, harming packaging and solder reliability.

4. Typical process parameters (production 6-inch GaAs backside gold)

5. Key differences from silicon wafer plating

1. Substrate: GaAs is brittle and corrodes electrochemically, so the bath pH window is narrow; silicon tolerates weak alkali and the process window is wide.

2. Bath: GaAs can only use sulphite gold; silicon can use cyanide gold.

3. Seed layer: GaAs has zero tolerance for pinholes, which directly cause substrate corrosion and scrap.

4. Thin-wafer handling: thinned GaAs warps very easily, so deposit stress control has very high priority.

5. TWV: GaAs vias have high aspect ratios, diffusion limitation is more pronounced, and pulse plating is practically required.