PROCESS DEMOS

Process basics, made simple.

The demos play automatically. Click a step or use ← → to move between steps, and Space to pause. Parameters shown are typical industry ranges.

PROCESS DEMO 01 / 04

GaAs backside via copper plating

RF chips ground their source through a via to a copper backside. The main steps from thinning and etching to plating, and what happens when the seed layer breaks on the lower via wall.

Schematic, not to scale

PROCESS DEMO 02 / 04

TGV process flow

Laser modification, wet etch, seed layer, butterfly fill, CMP and double-sided RDL, compared with a run where the via mouths close too early and trap voids.

Schematic, not to scale

PROCESS DEMO 03 / 04

TGV fill: where voids come from

Whether a via ends up void-free depends on what finishes first: the waist bridge, the growth front or the mouth closing. Three runs: well-balanced additives, weak suppression and no additives.

Schematic, not to scale

PROCESS DEMO 04 / 04

Plating cell and uniformity

Field lines, ions and flow in a fountain plating cell, with copper on a GaAs wafer and on a glass substrate. Field lines crowd at the wafer edge and thicken the deposit there; a shield ring flattens the profile. The last run shows a fouled cathode contact.

Schematic, not to scale

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