Controlling Deposit Stress in GaAs Wafer Electroplating

In GaAs wafer plating (sulphite gold), deposit stress comprises intrinsic deposition stress (grain defects from electrodeposition, co-deposited impurities), seed-film stress, thermal-mismatch stress and mechanical constraint stress in the thin wafer. Thinned GaAs (50-150 μm) has very low stiffness, so residual stress shows up directly as wafer warpage, deposit peeling, via cracking and focus failures in later lithography. Stress is usually measured with the Stoney equation, working back from wafer warpage to the residual stress in the deposit. Production target: keep residual stress in the gold deposit within -50~+50 MPa (close to zero), and avoid tensile or compressive stress above 100 MPa wherever possible.

Note: sulphite gold almost never reaches true zero stress; residual stress can only be held at a low level. High-temperature annealing (>250℃) is strictly prohibited: it causes interdiffusion at the GaAs/TiW/Au interface and device failure.

1. Main sources of stress

1. Intrinsic electrodeposition stress: excessive current density, over-refined grains, co-deposited impurities or brighteners and entrapped hydrogen produce high tensile stress; stress rises markedly as the bath ages and organic breakdown products accumulate.

2. Residual seed-layer stress: the sputtered TiW/Au film carries its own stress; with unsuitable sputter pressure, power or rate the seed alone can carry tens to 200 MPa, pushing the total stress with the plated layer out of specification.

3. Thermal stress: the difference between plating and room temperature, and the thermal-expansion mismatch between Au and GaAs (GaAs ≈ 5.7 ppm/℃, Au ≈ 14.2 ppm/℃), introduce thermal stress on cooling.

4. Mechanical constraint stress: stress in the temporary bonding adhesive, clamping forces on the wafer and excessive deposit thickness; stress grows roughly linearly with deposit thickness.

5. Edge effect: higher current density at the wafer edge gives a thicker, more stressed edge deposit and bowl-shaped warpage.

2. Bath and formulation control (sodium gold sulphite)

1. Strict windows for gold content, pH and temperature

• Au concentration: 10-13 g/L. Too little gold increases polarisation at the same current density and raises tensile stress; too much gives coarse grains.
• pH: 7.8-8.2 (the window must be narrow)
  • pH＞8.5: tensile stress rises markedly and the grain coarsens;
  • pH＜7.5: the GaAs substrate corrodes and compressive stress in the deposit increases.
• Temperature: 50-54℃, never above 58℃. Higher temperature means more thermal-mismatch stress; too low raises polarisation and intrinsic tensile stress. Hold constant within ±1℃.
• Buffers: citrate / phosphate buffer systems stabilise pH and suppress stress drift; analyse the bath regularly and control sulphite breakdown products.

2. Additive control

• Never overdose brighteners / grain refiners: co-deposited organics introduce very high tensile stress. Prefer low-stress sulphite gold additives and use strongly brightening formulations sparingly.
• Bath-life management: sulphite oxidises to sulphate and organic breakdown products accumulate, so stress keeps worsening with bath age. Treat regularly with activated carbon and dummy plating at low current to remove organic impurities.

Symptom: with the same parameters a fresh bath gives low stress, but after a few tens of Ah/L warpage increases. The cause is intrinsic stress rising with impurities.

3. Power waveform and electrical parameters (the most important process lever)

Low stress is hard to achieve with DC plating. Thick gold on GaAs in production generally uses pulse or periodic-reverse (PR) plating, which lowers intrinsic residual stress and also improves TWV step coverage.

Reference pulse-reverse parameters (6-inch GaAs backside gold, deposit 3-6 μm)

• Do not chase speed with high current; a low average current density is the basis of low stress in thick gold. Accept a longer plating time.
• Edge current effect: a current shield on the tool lowers the locally excessive current at the wafer edge and reduces edge stress concentration.

Agitation and flow

Horizontal rotating plating: 80-150 rpm with forced spray of the bath to thin the cathode diffusion layer. A thick diffusion layer causes local polarisation fluctuations, uneven grain and scattered stress.

4. Seed-layer (sputtered stack) stress control

Seed-layer stress adds directly to the total plated stress; many warpage problems originate not in plating but in the sputtered seed.

1. Standard stack: TiW (70-90 nm)/Au (100-130 nm); optionally the improved NiV/TiW/Au, balancing adhesion and low stress.

2. Sputter tuning: raise the Ar working pressure and moderately lower the deposition rate to reduce intrinsic tensile stress in TiW; avoid heavy ion bombardment, which produces high film stress.

3. Do not keep thickening the seed: above 150 nm of Au seed, the sputtered film stress rises markedly.

4. Plate soon after sputtering to avoid seed oxidation and stress drift with time.

5. Thickness design, temporary bonding and mechanical stress

1. Deposit thickness: stress grows roughly linearly with thickness. For RF backside ground, do not plate thicker gold than conduction and heat dissipation require; for example, if 4 μm is enough, do not plate 8 μm.

2. Low-stress temporary bonding adhesive: residual stress in the cured adhesive transfers to the thin GaAs wafer. Use semiconductor-grade low-stress temporary bonding adhesive and cure at the lowest practical temperature to avoid thermal stress in the adhesive.

3. Wafer holding: vacuum chucks in horizontal plating; no hard mechanical clamping, which introduces external mechanical stress.

4. Stress compensation (some TWV processes): if backside plating produces one-directional tensile stress, a low-stress film can be kept on the front side, where devices allow, to counter it and balance wafer bow.

6. Post-plating treatment (no high-temperature annealing on GaAs!)

Ordinary copper plating is often annealed at 200-300℃ to relieve stress. This does not apply to gold on GaAs wafers:

At 200℃, the TiW/Au and GaAs interface interdiffuses and forms intermetallics, causing device leakage and reliability failures; cooling down again introduces thermal stress.

✅ Permitted post-treatment:

1. Thorough overflow rinse after plating; low-temperature hot-air drying ≤80℃ with gradual cooling, no thermal shock.

2. Room-temperature ageing: leave the plated wafer at room temperature for a few hours; slight recrystallisation releases part of the intrinsic stress naturally before debonding and lithography. ❌ Prohibited: high-temperature baking, thermal annealing, rapid heating or cooling.

7. Common failures and countermeasures

8. Quick stress assessment on the line

1. Laser warpage gauge: measure warp before and after plating on the same bonded carrier and calculate deposit residual stress with the Stoney equation; this is the most direct method.

2. Controlled comparison: hold all else constant and change only current density or pulse parameters, comparing post-plating warpage; compare a fresh bath with an aged one to judge the contribution of bath impurities.

3. Elimination: sputter the seed only, without plating, and measure the warpage of carrier + GaAs, separating the stress from the seed layer from the stress introduced by plating.